This invention relates to equalization circuitry.
Signals received by a system component, such as a programmable logic device (“PLD”), may benefit from initial processing of the type known as equalization. For example, one objective of equalization may be to restore crispness or sharpness to level transitions in a received data or clock signal. The circuitry originating the signal may transmit it with sharp transitions, but the sharpness of those transitions may be degraded by the medium (e.g., printed circuit board (“PCB”) traces) through which the signal must travel to reach the receiver. Especially at very high data rates, it can be important for the receiver circuitry to first restore the sharpness to transitions in the received signal so that further circuitry of the receiver can process that signal properly and accurately at the high data rate. This is the (or at least one) function of equalization circuitry that may be included in the receiver.
Programmable logic devices (“PLDs”) are examples of circuit components that are typically made with the intention that they can be used in a wide variety of systems. The manufacturer of a PLD does not know the specifics of all the systems in which the PLD will be used. To give the PLD a large potential market, the manufacturer tries to give the PLD a wide range of capabilities. The user of the PLD can then customize the PLD to meet a user's particular needs by appropriately programming or otherwise controlling various aspects of the PLD's circuitry. Equalization is a capability that a PLD may be advantageously equipped with, and if so, then a wide range of equalization response, with flexible programmable or other control, is desirable. In this way the equalization circuitry of the PLD can be customized by a user to allow the PLD to compensate for many different types and/or degrees of degradation in a received signal.
One possible way to accomplish the foregoing is to provide several equalization cells on a PLD in series. Each of the equalization cells is programmable or otherwise controllable to some degree, and the number of cells that are connected in series may also be selectable (e.g., by programming or other control). A possible shortcoming of this approach is that to produce a higher-order response that may be needed for very high data rates, a larger-than-desirable number of equalization cells may need to be connected in series. Overall system performance may be degraded by such a circuit configuration.